/*********************************************************************************

    Auth: Jack.Pan
    Date: 2023/8/15
    Ver:  V1.0
    Desc: 
***********************************************************************************/
module e4fpmk7_mmb(
//-----------------on motherboard------------
    ////sd card
    //inout sd_cd,
    //inout [3:0] sd_d,
    //inout sd_clk,
    //inout sd_cmd,
    ////cs534x i2s adc
    //output adc_rst_n,
    //output adc_mclk,
    //inout  adc_sclk,
    //inout  adc_lrck,
    //input  adc_sdout,
    //output [1:0] adc_mode,
    ////cs43xx i2s dac
    //output dac_sclk,
    //output dac_lrck,
    //output dac_sdin,
    //output dac_mclk,
    ////ps2 interface
    //inout ps2_clk_1,    ps2_clk_2,
    //inout ps2_data_1,   ps2_data_2,
    // uart interface
    input uart_rxd,
    output uart_txd,
    //vga interface
    //output          vga_clk,
    //output [7:0]    vga_blue, vga_green, vga_red,
    //output          vga_sync_n,
    //output          vga_psave_n,   //0:7123 in power save mode
    //output          vga_blank_n, vga_hs, vga_vs,
    ////key
    //input [7:0]     key,
    ////but
    //input [7:0]     but,
    ////7-seg display
    //output          seg_g, seg_f, seg_e, seg_d, seg_c, seg_b, seg_a, seg_dp,
    //output [3:0]    seg_sel,
    ////led output
    output [7:0]    led,
    ////clock generate (CDCM 61002)
    //output [1:0]    clkgen_pr, clkgen_os,
    //output [2:0]    clkgen_od,
    ////gpio total 17*2
    //input [16:0]    gpio0, gpio1;
//--------------on SoM part----------------------
    ////eth phy
    //output          rgmii_reset_n,
    //inout           rgmii_mdio, rgmii_mdc,
    //input [3:0]     rgmii_rxd,
    //input           rgmii_rxck, rgmii_rxctl,
    //output          rgmii_txctl, rgmii_txck,
    //output[3:0]     rgmii_txd,
    ////  emmc
    //inout [7:0]     emmc_dq,
    //output          emmc_cmd, emmc_clk,emmc_rst_n,
    ////  user flash
    //output          qspi_cs_n,
    //inout [3:0]     qspi_dq,
    //output          qspi_sclk,
    //// user led & key
    output          som_led,
    input           som_key,
    // clock
    //input       ext_clk_27m,
    input       refclk_200m_p,
    input       refclk_200m_n
    ////usb phy (device)
    //input       usbd_clk, usbd_dir, usbd_nxt, usbd_stp,
    //inout [7:0] usbd_dq,
    ////usb phy (host)
    //input       usbm_clk, usbm_dir, usbm_nxt, usbm_stp,
    //inout [7:0] usbm_dq,
    ////hdmi (or GPIO)
    //inout           hdmi_scl, hdmi_sck,
    //output [2:0]    tmds_l_p, tmds_l_n,
    //output          tmds_clk_p, tmds_clk_n,
    ////pwm vid (CAUTION WHEN USE THIS SIGNAL)
    //output          pwmvid      //when use pwmvid, the dcdc converter must be set to pwmvid-ctrl mode
    //                            //the default config is fixed 1V output
);
//--------------clock and PLL-------------
    wire    clk_200m;
    wire    clk_100m;
    wire    CLKFBIN;
    wire    pll_lock;
//---------------cu signals------------------
    wire    FramingErrorOccurred;
    wire    ChunkRcvd;
    wire    DigestReady;
    wire    DigestTransmitted;

   // IBUFDS: Differential Input Buffer
   //         Kintex-7
   // Xilinx HDL Language Template, version 2019.2

   IBUFDS #(
      .DIFF_TERM("FALSE"),       // Differential Termination
      .IBUF_LOW_PWR("TRUE"),     // Low power="TRUE", Highest performance="FALSE" 
      .IOSTANDARD("DEFAULT")     // Specify the input I/O standard
   ) IBUFDS_inst (
      .O(clk_200m),  // Buffer output
      .I(refclk_200m_p),  // Diff_p buffer input (connect directly to top-level port)
      .IB(refclk_200m_n) // Diff_n buffer input (connect directly to top-level port)
   );

   // PLLE2_BASE: Base Phase Locked Loop (PLL)
   //             Kintex-7
   // Xilinx HDL Language Template, version 2019.2
   PLLE2_BASE #(
      .BANDWIDTH("OPTIMIZED"),  // OPTIMIZED, HIGH, LOW
      .CLKFBOUT_MULT(2),        // Multiply value for all CLKOUT, (2-64)
      .CLKFBOUT_PHASE(0.0),     // Phase offset in degrees of CLKFB, (-360.000-360.000).
      .CLKIN1_PERIOD(0.0),      // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
      // CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
      .CLKOUT0_DIVIDE(4),
      .CLKOUT1_DIVIDE(1),
      .CLKOUT2_DIVIDE(1),
      .CLKOUT3_DIVIDE(1),
      .CLKOUT4_DIVIDE(1),
      .CLKOUT5_DIVIDE(1),
      // CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
      .CLKOUT0_DUTY_CYCLE(0.5),
      .CLKOUT1_DUTY_CYCLE(0.5),
      .CLKOUT2_DUTY_CYCLE(0.5),
      .CLKOUT3_DUTY_CYCLE(0.5),
      .CLKOUT4_DUTY_CYCLE(0.5),
      .CLKOUT5_DUTY_CYCLE(0.5),
      // CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
      .CLKOUT0_PHASE(0.0),
      .CLKOUT1_PHASE(0.0),
      .CLKOUT2_PHASE(0.0),
      .CLKOUT3_PHASE(0.0),
      .CLKOUT4_PHASE(0.0),
      .CLKOUT5_PHASE(0.0),
      .DIVCLK_DIVIDE(1),        // Master division value, (1-56)
      .REF_JITTER1(0.0),        // Reference input jitter in UI, (0.000-0.999).
      .STARTUP_WAIT("FALSE")    // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
   )
   PLLE2_BASE_inst (
      // Clock Outputs: 1-bit (each) output: User configurable clock outputs
      .CLKOUT0      (clk_100m),   // 1-bit output for main clock (75MHz)
      .CLKOUT1      (),   // 1-bit output for 25MHz VGA clock
      .CLKOUT2      (),   // 1-bit output: CLKOUT2
      .CLKOUT3      (),   // 1-bit output: CLKOUT3
      .CLKOUT4      (),   // 1-bit output: CLKOUT4
      .CLKOUT5      (),   // 1-bit output: CLKOUT5
      // Feedback Clocks: 1-bit (each) output: Clock feedback ports
      .CLKFBOUT     (CLKFBIN), // 1-bit output: Feedback clock
      .LOCKED       (pll_lock),     // 1-bit output: LOCK
      .CLKIN1       (clk_200m),     // 1-bit input: Input clock
      // Control Ports: 1-bit (each) input: PLL control ports
      .PWRDWN       (1'b0),     // 1-bit input: Power-down
      .RST          (som_key),           // 1-bit input: Reset
      // Feedback Clocks: 1-bit (each) input: Clock feedback ports
      .CLKFBIN      (CLKFBIN)    // 1-bit input: Feedback clock
   );

sha256_cu                   cu(
    .Clk                    (clk_100m),
    .Reset                  (!pll_lock),
    .Rx                     (uart_rxd),
    .Tx                     (uart_txd),
    .FramingErrorOccurred   (FramingErrorOccurred), 
    .ChunkRcvd              (ChunkRcvd),
    .DigestReady            (DigestReady), 
    .DigestTransmitted      (DigestTransmitted), 
    .WOut                   (), 
    .CurrentHash            ()
);
assign led[0] = pll_lock;
assign led[1] = ChunkRcvd;
assign led[2] = DigestReady;
assign led[3] = DigestTransmitted;
assign led[4] = FramingErrorOccurred;
assign led[7:5] = 3'b0;


endmodule